Patent-2: Taiwan Patent No. TW M680973 U.  Name: Random Access Memory with Two-Terminal Memory Cells.  Application Date: 2025/10/29.  Granted Date: 2026/03/11.  Patent Family: Ongoing.

Application: Embedded Memory inside IC Integrated Circuits Chips, Independent IC Memory Chips.

Referring to Fig.1, a prior art is a memory cell MC of random access memory as shown in Fig.1, which is a random access memory cell includes one MTJ (Magnetic Tunnel Junction) memory element, one transistor MSW, and three terminal wires. The three terminal wires are the word line WL, the bit line BL, and the select line SL. The magnetic tunnel junction memory element MTJ is used to store data. The word line WL and the bit line BL are used to select the magnetic tunnel junction memory element MTJ. The transistor MSW is used as a selection control switch for the magnetic tunnel junction memory element MTJ. The select line SL and the bit line BL are used for the read and write voltage signal control of the stored data of the magnetic tunneling junction memory element MTJ. But, the prior art's transistor MSW and three terminal wires cause the memory cell to occupy a fixed area of ​​the chip substrate, making it difficult to achieve high density of random access memory or to stack memory cells in three dimensions.

This patent proposes a random access memory cell includes only one memory element, one diode and two terminal wires. Furthermore, the random access memory cell array proposed in this patent is not affected by the data stored in other memory cells besides the operating memory cell during operation, nor does it affect the data stored in other memory cells besides the operating memory cell. The random access memory cell proposed in this patent, which includes only one memory element, one diode and two terminal wires, occupies a smaller chip substrate area than the random access memory cell of the prior art that includes one memory element, one transistor and three terminal wires. Therefore, the density of random access memory can be increased with the same chip substrate area, saving costs and making it easier to stack memory cells in three dimensions.