Patent-1: Taiwan Patent No. TW M678655 U.  Name: Random Access Memory.  Application Date: 2025/10/13.  Granted Date: 2025/12/21.  Patent Family: Ongoing.

Application: Embedded Memory inside IC Integrated Circuits Chips, Independent IC Memory Chips.

Introduction:

Operating conditions of the memory cell array in the embodiments of this patent allow the memory cell being manipulated to be correctly subjected to the operation. Furthermore, the data stored in other memory cells connected to the same write word line and select word line, or in several memory cells connected to other write word lines and select word lines will not be affected. The random access memory of this patent has the advantages of fewer memory cell wires, a smaller chip substrate area, and no need for additional 3D capacitor manufacturing processes compared to prior art random access memory.

The prior art proposed a memory cell for random access memory as shown in Fig.1, which is a random access memory cell includes 3 transistors and 5 wires. The three transistors are the write transistor MW, the data storage transistor MDS, and the read transistor MR. The five wires are the read word line RWL, the write word line WWL, the read bit line RBL, the write bit line WBL, and the ground line GND. The specific state of the storage gate SG causes the data storage transistor MDS to store data. But, the five wires of the prior art would cause the memory cell to occupy a fixed area of ​​the chip substrate.

In this patent, to overcome the drawback of the prior art, where random access memory cell includes three transistors and five wires occupy a large fixed chip substrate area, this patent proposes a random access memory cell comprising only three wires. Furthermore, the random access memory cell array proposed in this patent is not affected by the data stored in other memory cells besides the operating memory cell during operation, nor does it affect the data stored in other memory cells besides the operating memory cell. The random access memory cell proposed in this patent, which has only 3 wires, occupies a smaller chip substrate area than the random access memory cell with 5 wires in the prior art. Therefore, the density of random access memory cells can be increased with the same chip substrate area, thus saving costs.